This invention relates generally to memory systems, and more particularly to memory systems which include a memory buffer that serves as an interface between a host controller and the RAM chips (typically DRAM) residing on a DIMM, the memory buffer being optionally located on the DIMM itself or as part of the motherboard on which the DIMM connectors are also located.
Traditional computer systems, such as servers, workstations, desktops and laptops, all use pluggable memory which can be inserted into slots on the computer's motherboard as needed. As shown in FIG. 1, the most common form of pluggable memory 10 is the Dual In-line Memory Module (DIMM). Historically, DIMMs contain multiple RAM chips—typically DRAM—each of which has a data bus width of 4 or 8 bits. Typically, eight or nine 8-bit DRAM chips 12 (or twice as many 4-bit DRAM chips) are arranged in parallel to provide each DIMM 16 and 18 with a total data bus width of 64 or 72 bits; the data bus, typically referred to as the ‘DQ’ bus, is connected to a host controller 14. Each arrangement of 64 or 72 data bits using DRAM chips 12 in parallel is termed a ‘rank’.
A command/address (CA) bus also runs between the host controller 14 and each DIMM 16 and 18; the CA and DQ busses together form a ‘system’ bus. With a basic unbuffered DIMM 16, the CA bus is connected to every DRAM 12 on the DIMM 16. As a result, there is a high electrical load on the CA bus, given by the product of the number of DRAMs times the number of ranks For the DQ bus, the number of electrical loads is equal to the number of ranks.
A buffering device is employed to reduce loading in a ‘load reduction’ DIMM (LR-DIMM), an example of which is illustrated in FIG. 2. An LR-DIMM 20 containing multiple DRAM chips 12 uses a logic device 22 to buffer the DQ and CA signals between the DRAMs 12 and a host controller 14. Logic device 22 may be, for example, a single device such as the iMB (isolating Memory Buffer) from Inphi Corporation. Memory systems of this sort are described, for example, in co-pending U.S. patent application Ser. Nos. 12/267,355 and 12/563,308, which are incorporated herein by reference, for all purposes.